In the prior art of semiconductor memory apparatus, SI.sub.1 I.sub.2 M layered structures have been used as memory devices. Here, "S" denotes a semiconductor substrate or layer; "I.sub.1 " and "I.sub.2 " denote first and second insulator layers, respectively; and "M" denotes a metal electrode layer. For electrical erase of this SI.sub.1 I.sub.2 M structure, a positive voltage is applied to the metal electrode, so that the captured electrons (if any) are transported back to the metal by means of Fowler-Nordheim tunneling in the opposite direction from that during the write-in. In such a memory device, the presence versus absence of captured electrons at surface states at the I.sub.1 I.sub.2 interface of the insulator layers defines the memory state of the device.
Other types of SI.sub.1 I.sub.2 M structures in the prior art rely upon the phenomenon of tunneling of charge carriers between the I.sub.1 I.sub.2 interface and the semiconductor, rather than the metal electrode. Again, the presence versus absence of captured electrons at the I.sub.1 I.sub.2 interface state defines the memory state of the device.
The above-mentioned SI.sub.1 I.sub.2 M structures can be incorporated in integrated circuit arrays for mass memories, as known in the art. In such arrays, instead of measuring capacitance of a two-terminal device as previously described, each of the I.sub.1 I.sub.2 M portions of many such SI.sub.1 I.sub.2 M structures is advantageously fabricated as the gates of insulated gate field effect transistors (IGFET's), in which the gates are all integrated on a single semiconductor substrate. As also known in the art, these arrays can be addressed for selective write-in, readout, and erase by various selective crosspoint electrical circuit techniques, such as described for example in U.S. Pat. No. 3,665,423 issued to S. Nakanuma et al. on May 23, 1972.
As set forth in U.S. Pat. No. 3,877,054, issued to Boulin et al. on Apr. 8, 1975, the interface states in the region of the I.sub.1 I.sub.2 interface of SI.sub.1 I.sub.2 M memory devices can be controlled and stabilized by introducing dispersed impurity metal atoms such as tungsten, in a surface concentration between about 10.sup.14 and 2 .times. 10.sup.15 per square centimeter the interface region. By "dispersed" is meant that the impurities do not clump or cluster together, which would form a Fermi level characteristic of the impurity itself. These impurity atoms also serve to increase the capture (trapping) efficiency of electronic charge carriers (electrons or holes), particularly those charge carriers which can be transported from the semiconductor (or metal) to the I.sub.1 I.sub.2 interface region by the phenomenon of Fowler-Nordheim tunneling to the interface states.
In the aforementioned Boulin et al. U.S. Pat. No. 3,877,054, it was suggested to introduce tungsten impurities by evaporation techniques or by purposely including a mixture of some tungsten halide impurites with an aluminum halide advantageously only during an initial stage of chemical vapor deposition of aluminum oxide as the I.sub.2 layer. However, tungsten evaporation techniques entail the use of relatively large amounts of costly ultra-pure tungsten sources (when compared to the exceedingly small amounts of tungsten deposited in the I.sub.1 I.sub.2 interface), high evaporation temperatures (in excess of 3000.degree.C), which consumes large amounts of energy, and furthermore require careful and skilled operators to control the process. Moreover, the inclusion of tungsten halide as an impurity in the initial phase of chemical vapor deposition of aluminum oxide tends to produce an I.sub.2 layer of poor electrical quality, thereby degrading charge storage times in the final device. Therefore it would be desirable to have more economical and easily controllable techniques for introducing metallic impurities, such as tungsten, into an I.sub.1 I.sub.2 interface region of a SI.sub.1 I.sub.2 M memory device.